Organic light-emitting diode display with external compensation and anode reset

ABSTRACT

A display may include an array of organic light-emitting diode display pixels having transistors characterized by threshold voltages subject to transistor variations. Compensation circuitry may be used to measure a transistor threshold voltage for a pixel. The threshold voltage may be sampled by controlling the pixel to sample the threshold voltage onto a capacitor at the pixel. The pixel may include at least one semiconducting-oxide transistor, silicon transistors, and a light-emitting diode. The diode may be coupled to a data line that can be used for both data loading and compensation sensing operations. Reset operations may be performed after data programming and before emission to reset the anode voltage for the diode.

This application is a continuation of patent application Ser. No. 15/802,367, filed Nov. 2, 2017, which claims the benefit of provisional patent application No. 62/476,562, filed on Mar. 24, 2017, which are hereby incorporated by reference herein in their entireties.

BACKGROUND

This relates generally to electronic devices with displays and, more particularly, to display driver circuitry for displays such as organic-light-emitting diode displays.

Electronic devices often include displays. For example, cellular telephones and portable computers include displays for presenting information to users.

Displays such as organic light-emitting diode displays have an array of display pixels based on light-emitting diodes. In this type of display, each display pixel includes a light-emitting diode and thin-film transistors for controlling application of a signal to the light-emitting diode to produce light.

An organic light-emitting diode display pixel includes a drive thin-film transistor connected to a data line via an access thin-film transistor. The access transistor may have a gate terminal that receives a scan signal via a corresponding scan line. Image data on the data line can be loaded into the display pixel by asserting the scan signal to turn on the access transistor. The display pixel includes a current source transistor that provides current to the organic light-emitting diode to produce light.

Transistors in an organic light-emitting diode display pixel may be subject to process, voltage, and temperature (PVT) variations. Due to such variations, transistor threshold voltages between different display pixels may vary. Variations in transistor threshold voltages can cause the display pixels to produce amounts of light that do not match a desired image. Compensation schemes are sometimes used to compensate for variations in threshold voltage. Such compensation schemes typically involve sampling operations that are performed within each pixel during normal display operations and thus increase the time required to display images.

It is within this context that the embodiments herein arise.

SUMMARY

An electronic device may include a display having an array of display pixels. The display pixels may be organic light-emitting diode display pixels. Each display pixel may have an organic light-emitting diode that emits light. A drive transistor (i.e., a current source transistor) in each display pixel may apply current to the organic light-emitting diode in that display pixel. The drive transistor may be characterized by a threshold voltage.

The threshold voltage may be subject to transistor variations. Compensation circuitry may be used to measure the threshold voltage of the drive transistor. The threshold voltage may be sampled by controlling the drive transistor to sample the threshold voltage onto a capacitor coupled between gate and source terminals of the current source transistor. The compensation circuitry may include sense circuitry that may be operated in combination with the pixel to transfer charge from the capacitor to the sense circuitry such that the threshold voltage is produced at an output of the sense circuitry. The compensation circuitry may generate compensation data based on the measured threshold voltage. During display operations, data circuitry may receive digital image data and process the digital image data along with the compensation data to generate analog data signals for the pixel.

Threshold voltage compensation data may be generated for each pixel or for groups of pixels. The compensation data may be stored in memory such as volatile or non-volatile memory. The compensation data may be stored as an offset value (e.g., normalized against a reference threshold voltage). During display operations, data circuitry may add the offset value to the digital image data. The summed digital value may be used in generating analog pixel data signals that compensates for threshold voltage variations between pixels.

The display pixel may also include an emission control transistor (e.g., a transistor that is coupled in series with the drive transistor and the light-emitting diode), a gate voltage setting transistor (e.g., a transistor for setting the gate terminal of the drive transistor to a predetermined reference voltage level), a data loading transistor (e.g., a transistor for loading data into the pixel and also for sensing the threshold voltage of the drive transistor), and an anode resetting transistor (e.g., a transistor for resetting the anode terminal of the light-emitting diode). A data programming operation may be followed by an anode resetting operation. The anode resetting operation can help eliminate the low gray non-uniformity issues, eliminate low refresh rate flicker, and improve variable refresh rate index.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an illustrative electronic device having a display in accordance with an embodiment.

FIG. 2 is a diagram of an illustrative display having an array of organic light-emitting diode display pixels coupled to compensation circuitry in accordance with an embodiment.

FIG. 3 is a circuit diagram of an illustrative display pixel formed from n-channel thin-film transistors in accordance with an embodiment.

FIG. 4 is a timing diagram illustrating relevant waveforms in operating the display pixel shown in FIG. 3 in accordance with an embodiment.

FIGS. 5A and 5B are timing diagrams illustrating how anode reset can help eliminate anode charging non-uniformity issues at low gray levels in accordance with an embodiment.

FIG. 6A is a diagram showing how at least some row control lines can be shared between pixels in adjacent rows in accordance with an embodiment.

FIG. 6B is a timing diagram illustrating relevant waveforms in operating display pixels with shared row control lines in accordance with an embodiment.

FIG. 7 is a circuit diagram of an illustrative display pixel formed from n-channel semiconducting-oxide transistors and p-channel silicon transistors in accordance with an embodiment.

FIG. 8 is a timing diagram illustrating relevant waveforms in operating the display pixel shown in FIG. 7 in accordance with an embodiment.

FIG. 9A is a diagram showing how at least some row control lines can be shared between adjacent pixels of the type shown in FIG. 7 in accordance with an embodiment.

FIG. 9B is a timing diagram illustrating relevant waveforms in operating the display pixels shown in FIG. 9A in accordance with an embodiment.

FIG. 10 is a flow chart of illustrative steps for operating a display pixel of the type shown in connection with FIGS. 2-9 in accordance with at least some embodiments.

DETAILED DESCRIPTION

An illustrative electronic device of the type that may be provided with an organic light-emitting diode (OLED) display is shown in FIG. 1. As shown in FIG. 1, electronic device 10 may have control circuitry 16. Control circuitry 16 may include storage and processing circuitry for supporting the operation of device 10. The storage and processing circuitry may include storage such as hard disk drive storage, nonvolatile memory (e.g., flash memory or other electrically-programmable-read-only memory configured to form a solid state drive), volatile memory (e.g., static or dynamic random-access-memory), etc. Processing circuitry in control circuitry 16 may be used to control the operation of device 10. The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio codec chips, application specific integrated circuits, programmable integrated circuits, etc.

Input-output circuitry in device 10 such as input-output devices 12 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 12 may include buttons, joysticks, click wheels, scrolling wheels, touch pads, key pads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user can control the operation of device 10 by supplying commands through input-output devices 12 and may receive status information and other output from device 10 using the output resources of input-output devices 12.

Input-output devices 12 may include one or more displays such as display 14. Display 14 may be a touch screen display that includes a touch sensor for gathering touch input from a user or display 14 may be insensitive to touch. A touch sensor for display 14 may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, a light-based touch sensor, or other suitable touch sensor arrangements.

Control circuitry 16 may be used to run software on device 10 such as operating system code and applications. During operation of device 10, the software running on control circuitry 16 may display images on display 14 in input-output devices.

FIG. 2 shows display 14 and associated display driver circuitry 15. Display 14 includes structures formed on one or more layers such as substrate 24. Layers such as substrate 24 may be formed from planar rectangular layers of material such as planar glass layers. Display 14 may have an array of display pixels 22 for displaying images to a user. The array of display pixels 22 may be formed from rows and columns of display pixel structures on substrate 24. These structures may include thin-film transistors such as polysilicon thin-film transistors, semiconducting oxide thin-film transistors, etc. There may be any suitable number of rows and columns in the array of display pixels 22 (e.g., ten or more, one hundred or more, or one thousand or more).

Display driver circuitry such as display driver integrated circuit 15 may be coupled to conductive paths such as metal traces on substrate 24 using solder or conductive adhesive. If desired, display driver integrated circuit 15 may be coupled to substrate 24 over a path such as a flexible printed circuit or other cable. Display driver integrated circuit 15 (sometimes referred to as a timing controller chip) may contain communications circuitry for communicating with system control circuitry 16 over path 125. Path 125 may be formed from traces on a flexible printed circuit or other cable. Control circuitry 16 (see FIG. 1) may be located on a main logic board in an electronic device such as a cellular telephone, computer, television, set-top box, media player, portable electronic device, or other electronic equipment in which display 14 is being used.

During operation, the control circuitry may supply display driver integrated circuit 15 with information on images to be displayed on display 14. To display the images on display pixels 22, display driver integrated circuit 15 may supply clock signals and other control signals to display driver circuitry such as row driver circuitry 18 and column driver circuitry 20. For example, data circuitry 17 may receive image data and process the image data to provide pixel data signals to display 14. The pixel data signals may be demultiplexed by column driver circuitry 20 and pixel data signals D may be routed to each pixel 22 over data lines 26 (e.g., to each red, green, or blue pixel). Row driver circuitry 18 and/or column driver circuitry 20 may be formed from one or more integrated circuits and/or one or more thin-film transistor circuits.

Display driver integrated circuit 15 may include compensation circuitry 17 that helps to compensate for variations among display pixels 22 such as threshold voltage variations. Compensation circuitry 17 may, if desired, also help compensate for transistor aging. Compensation circuitry 17 may be coupled to pixels 22 via path 19, switching circuitry 21, and paths 23. Compensation circuitry 17 may include sense circuitry 25 and bias circuitry 27. Sense circuitry 25 may be used in sensing (e.g., sampling) voltages from pixels 22. During sense operations, switching circuitry 21 may be configured to electrically couple sense circuitry 25 to one or more selected pixels 22. For example, compensation circuitry 17 may produce control signal CTL to configure switching circuitry 21. Sense circuitry 25 may sample voltages such as threshold voltages or other desired signals from the pixels over path 19, switching circuitry 21, and paths 23. Bias circuitry 27 may include one or more driver circuits for driving reference or bias voltages onto nodes of pixels 22. For example, switching circuitry 21 may be configured to electrically couple path 19 to one or more selected pixels 22. In this scenario, bias circuitry 27 may provide reference signals to the selected pixels. The reference signals may bias nodes at the selected pixels at desired voltages for the sensing operations performed by sense circuitry 25.

Compensation circuitry 17 may perform compensation operations on pixels 22 using bias circuitry 27 and sense circuitry 25 to generate compensation data that is stored in storage 29. Storage 29 may, for example, be static random access memory (SRAM). In the example of FIG. 2, storage 29 is on-chip storage. If desired, storage 29 may be off-chip storage such as non-volatile storage (e.g., non-volatile memory that maintains stored information even when the display is powered off). The compensation data stored in storage 29 may be retrieved by data circuitry 13 during display operations. Data circuitry 13 may process the compensation data along with incoming digital image data to generate compensated data signals for pixels 22.

Data circuitry 13 may include gamma circuitry 44 that provides a mapping of digital image data to analog data signals at appropriate voltage levels for driving pixels 22. Multiplexer 46 receives a set of possible analog data signals from gamma circuitry 44 and is controlled by the digital image data to select an appropriate analog data signal for the digital image data. Compensation data retrieved from storage 29 may be added to (or subtracted from) the digital image data by adder circuit 48 to help compensate for transistor variations (e.g., threshold voltage variations, transistor aging variations, or other types of variations) between different display pixels 22. This example in which compensation data is added as an offset to digital input image data is merely illustrative. In general, data circuitry 13 may process compensation data along with image data to produce compensated analog data signals for driving pixels 22.

In contrast to techniques that focus on performing in-pixel threshold canceling (such as by performing a reset phase followed by a threshold compensation phase), performing compensation in this way using compensation circuitry 17 outside of each pixel 22 allows for higher refresh rates (e.g., greater than 60 Hz refresh rate, at least 120 Hz refresh rate, etc.) and is sometimes referred to as “external” compensation. External variation compensation may be performed in the factory, in real time (e.g., during blanking intervals between successive image frames), or when the display is idle (as examples).

Row driver circuitry 18 may be located on the left and right edges of display 14, on only a single edge of display 14, or elsewhere in display 14. During operation, row driver circuitry 18 may provide row control signals on horizontal lines 28 (sometimes referred to as row lines, “scan” lines, and/or “emission” lines). Row driver circuitry may include scan line driver circuitry for driving the scan lines and emission driver circuitry for driving the emission lines.

Demultiplexing circuitry 20 may be used to provide data signals D from display driver integrated circuit (DIC) 15 onto a plurality of corresponding vertical lines 26. Demultiplexing circuitry 20 may sometimes be referred to as column driver circuitry, data line driver circuitry, or source driver circuitry. Vertical lines 26 are sometimes referred to as data lines. During display operations, display data may be loaded into display pixels 22 using lines 26.

Each data line 26 is associated with a respective column of display pixels 22. Sets of horizontal signal lines 28 run horizontally through display 14. Each set of horizontal signal lines 28 is associated with a respective row of display pixels 22. The number of horizontal signal lines in each row is determined by the number of transistors in the display pixels 22 that are being controlled independently by the horizontal signal lines. Display pixels of different configurations may be operated by different numbers of scan lines.

Row driver circuitry 18 may assert control signals such as scan and emission signals on the row lines 28 in display 14. For example, driver circuitry 18 may receive clock signals and other control signals from display driver integrated circuit 15 and may, in response to the received signals, assert scan control signals and an emission control signal in each row of display pixels 22. Rows of display pixels 22 may be processed in sequence, with processing for each frame of image data starting at the top of the array of display pixels and ending at the bottom of the array (as an example). While the scan lines in a row are being asserted, control signals and data signals that are provided to column driver circuitry 20 by DIC 15 may direct column driver circuitry 20 to demultiplex and drive associated data signals D (e.g., compensated data signals provided by data circuitry 13) onto data lines 26 so that the display pixels in the row will be programmed with the display data appearing on the data lines D. The display pixels can then display the loaded display data.

In an organic light-emitting diode display, each display pixel 22 contains a respective organic light-emitting diode. A circuit diagram of an illustrative organic light-emitting diode display pixel 22 that is coupled to compensation circuitry 17 is shown in FIG. 3. As shown in FIG. 3, display pixel 22 may include a light-emitting diode 300, n-channel thin-film transistors 310, 312, 314, 316, and 318, and a storage capacitor Cst1. In particular, transistor 312 is sometimes referred to as the “drive” transistor. Transistors 310 and 312 and diode 300 may be coupled in series between a first power supply line 302 (e.g., a positive power supply line on which positive power supply voltage VDDEL is provided) and a second power supply line 304 (e.g., a ground power supply line on which ground voltage VSSEL is provided). Transistor 310 has a gate terminal that receives an emission control signal EM provided over emission control line 28-4; transistor 310 is therefore sometimes referred to as an emission control transistor. Storage capacitor Cst1 may have first and second terminals that are coupled to gate and source terminals of drive transistor 312, respectively.

Transistor 314 may be coupled between vertical line 23 (e.g., a shared path on which a reference voltage Vref is provided to each pixel 22 along a given column) and the gate (G) of drive transistor 312. Transistor 314 has a gate terminal that receives scan control signal SCAN1 and is selectively turned on to set the gate voltage of drive transistor 312 to a predetermined voltage level (e.g., to voltage level Vref). Transistor 314 is therefore sometimes referred to as a gate voltage setting transistor.

Transistor 316 may be coupled between vertical line 26 (e.g., a data line that is coupled to column driver circuitry 20) and the anode terminal of diode 300. Transistor 316 has a gate terminal that receives scan control signal SCAN2 and is selectively turned on to load a data signal into pixel 22. Transistor 316 is therefore sometimes referred to as a data loading transistor.

Transistor 318 may be coupled between reference voltage line 23 and the anode terminal of the light-emitting diode 300. Transistor 318 has a gate terminal that receives scan control signal SCAN3 and is selectively turned on to reset the anode of diode 300 to reference voltage level Vref. Transistor 318 is therefore sometimes referred to as an anode resetting transistor.

With one suitable arrangement, which is sometimes described herein as an example, the channel region (active region) in some thin-film transistors on display 14 is formed from silicon (e.g., silicon such as polysilicon deposited using a low temperature process, sometimes referred to as “LTPS” or low-temperature polysilicon), whereas the channel region in other thin-film transistors on display 14 is formed from a semiconducting oxide material (e.g., amorphous indium gallium zinc oxide, sometimes referred to as “IGZO”). If desired, other types of semiconductors may be used in forming the thin-film transistors such as amorphous silicon, semiconducting oxides other than IGZO, etc. In a hybrid display configuration of this type, silicon transistors (e.g., LTPS transistors) may be used where attributes such as switching speed and good drive current are desired (e.g., for gate drivers in liquid crystal diode displays or in portions of an organic light-emitting diode display pixel where switching speed is a consideration), whereas oxide transistors (e.g., IGZO transistors) may be used where low leakage current is desired (e.g., in liquid crystal diode display pixels and display driver circuitry) or where high pixel-to-pixel uniformity is desired (e.g., in an array of organic light-emitting diode display pixels). Other considerations may also be taken into account (e.g., considerations related to power consumption, real estate consumption, hysteresis, etc.).

Oxide transistors such as IGZO thin-film transistors are generally n-channel devices (i.e., NMOS transistors). Silicon transistors can be fabricated using p-channel or n-channel designs (i.e., LTPS devices may be either PMOS or NMOS). Combinations of these thin-film transistor structures can provide optimum performance.

In the example of FIG. 3, transistor 314 may be a semiconducting-oxide transistor, while the other transistors 310, 312, 316, and 318 are silicon transistors (e.g., n-channel LTPS transistors). Since the impedance at the gate (G) of drive transistor 312 is high, having semi-conducting oxide transistor 314 being coupled to that node may be advantageous to help reduce leakage and power consumption.

In the arrangement of FIG. 3, not only is data loading performed using line 26, but current sensing can also be performed on data line 26. In other words, sensing circuitry 25 of compensation circuitry 17 shown in FIG. 1 might share the same data lines 26 with the data programming circuitry. If data programming and current sensing were not performed on the same data line 26, it will be necessary to include a separate sensing path for each pixel column (i.e., line 23 will need to also support current sensing), which would substantially increase array routing complexity and area. Thus, performing data programming and current sensing via data lines 26 can help dramatically reduce array routing complexity and area, because a global reference voltage line 23 can be coupled to each pixel column (e.g., reference line 23 might be shared among the different columns in the display pixel array).

FIG. 4 is a timing diagram illustrating relevant waveforms in operating display pixel 22 shown in FIG. 3. Prior to time t1, only signal EM is asserted (e.g., emission control signal EM is driven high to logic “1”) while all other scan control signals SCAN1, SCAN2, and SCAN3 are deasserted (e.g., the scan control signals are driven low to logic “0”) for that row. The period during which signal EM is asserted may be referred to as the emission period T_(EMISSION) or the emission phase.

At time t2, scan signal SCAN1 may be asserted to turn on transistor 314. Activating transistor 314 may allow the gate of drive transistor 312 to be set to the reference voltage level Vref. At time t3, scan signal SCAN2 may be asserted to turn on transistor 316. Activating transistor 316 may allow a data signal presented along line 26 to be loaded into the display pixel (e.g., the data signal may be loaded onto the anode terminal of light-emitting diode 300). The value of the data signal at the falling edge of signal SCAN2 (at time t4) determines what is actually loaded into the display pixel. The period between time t2 and t4 may be referred to as the data programming period T_(DATA_PROGRAMMING) or the data writing phase. The duration of time that the current data signal should be held constant for that row is indicated as one unit programming time 1H (shown as T_(PROG)).

At time t5, signal SCAN1 is deasserted. At this point, the voltage across capacitor Cst1 is fixed (e.g., the voltage stored in Cst1 is equal to the difference between Vref and the programmed data value).

At time t6, only scan signal SCAN3 may be asserted to turn on transistor 318. Activating transistor 318 may allow the anode of light-emitting diode 300 to be reset to reference voltage level Vref. Because transistor 314 is turned off, the voltage across capacitor Cst1 cannot change at this time. Thus, resetting the anode voltage level to Vref will simply shift the gate level of drive transistor 312 up (or down) by the difference between Vref and the data value just loaded into the anode. The gate-to-source voltage of drive transistor 312 should not change. At time t7, scan signal SCAN3 is deasserted. The period between time t6 and t7 may be referred to as the anode reset period T_(ANODE_RESET) or the anode reset phase. In this example, assertions of scan control signals SCAN1 and SCAN2 are overlapping in time, whereas assertions of scan control signals SCAN1 and SCAN3 are non-overlapping in time.

At time t8, emission control signal EM may be asserted for the emission phase. During the emission phase, current will flow through transistors 310 and 312 and light-emitting diode 300, where the magnitude of the current is dependent on the voltage stored across capacitor Cst1. The amount of current will affect the actual luminance of light that is emitted from diode 300.

FIGS. 5A and 5B are timing diagrams illustrating how performing anode reset can help eliminate anode charging non-uniformity issues at low gray levels. FIG. 5A plots the anode voltage level as a function of time. Voltage level V_(ON) represents the OLED turn-on voltage threshold. Waveform 500 represents the anode voltage level if the data signal is set to a first gray level V1. Waveform 502 represents the anode voltage level if the data signal is set to a second gray level V2. As shown in FIG. 5A, the voltage of the anode will charge up but will reach threshold V_(ON) at different times. Thus, the emission period T_(E1) associated with waveform 500 and the emission period T_(E2) associated with waveform 502 will be slightly different, resulting in anode charging non-uniformity. FIG. 5B shows how this will negatively impact average brightness levels since the emission periods will be different for pixels with different gray levels. This issue is exacerbated at low gray levels.

In accordance with an embodiment, performing anode reset after data loading and before emission eliminates the low gray non-uniformity issue. Moreover, the anode reset operation can help mimic high frequency refresh rates (e.g., 60 Hz, 120 Hz, etc.) even when the display is only operating at low refresh rates (e.g., 30 Hz or below), thus eliminating low refresh rate flicker and improving variable refresh rate index.

FIG. 6A is a diagram showing how at least some row control lines can be shared between pixels in adjacent rows. As shown in FIG. 6A, a gate driver stage such as stage 600 may drive row control signals SCAN1, SCAN3, and EM that is shared between pixels 22-1 and 22-2 and other pixels in the two rows and may also drive signal SCAN2_ODD that is fed only to pixel 22-1 and other pixels in the first row and signal SCAN2_EVEN that is fed only to pixel 22-2 and other pixels in the second row. Gate driver stage 600 may represent one stage in a chain of stages in row driver circuitry 18 (see FIG. 2). While signals SCAN1, SCAN3, and EM can be shared among multiple adjacent rows, signal SCAN2 cannot be shared since it controls the data loading (e.g., different pixels need to be loaded with different data signals to maintain full display resolution).

FIG. 6B is a timing diagram illustrating relevant waveforms in operating display pixels with shared row control lines, as shown in configuration of FIG. 6A. Prior to time t1, only signal EM is asserted while all other scan control signals SCAN1, SCAN2_ODD, SCAN2_EVEN, and SCAN3 are deasserted for those two rows.

At time t2, shared scan signal SCAN1 may be asserted to turn on transistor 314 in both pixels 22-1 and 22-2 (see FIG. 6A). At time t3, scan signal SCAN2_ODD may be asserted to turn on transistor 316 in pixel 22-1 (and other pixels along that row). At time t4, scan signal SCAN2_EVEN may be asserted to turn on transistor 316 in pixel 22-2 (and other pixels along that row). At time t5, signal SCAN2_ODD may be deasserted to latch data signal “A” into pixel 22-1. At time t6, signal SCAN2_EVEN may be deasserted to latch data signal “B” into pixel 22-2. At time t7, signal SCAN1 may be deasserted.

At time t8, shared scan signal SCAN3 may be asserted to turn on transistor 318 in both pixels 22-1 and 22-2 to perform the anode reset operation. At time t9, signal SCAN3 may be deasserted. At time t10, shared emission control signal EM may be asserted to start the emission phase. The exemplary timing scheme of FIG. 6B in which the emission period is 8H in duration (i.e., eight times the unit data programming period), the SCAN1 period is 4H, and the SCAN2 and SCAN3 periods are 1.5H is merely illustrative and does not serve to limit the scope of the present embodiment. If desired, these periods can be lengthened or shorted and shifted forward or backward in time, so long as data programming and anode reset is properly performed. In general, the sharing of row control lines may be extended to any number of adjacent rows (e.g., row control lines may be shared among three or more rows, four or more rows, five or more rows, etc.).

FIG. 7 shows another suitable arrangement in which pixel 22 includes n-channel semiconducting-oxide transistors and p-channel silicon transistors, where pixel 22 may be coupled to compensation circuitry 17 of FIG. 2. As shown in FIG. 7, display pixel 22 may include a light-emitting diode 300, n-channel thin-film transistors 312′ and 314, p-channel thin-film transistors 310′, 316′, and 318′, and storage capacitor Cst1. Transistor 312′ may be referred to as the “drive” transistor. Transistors 310′ and 312′ and diode 300 may be coupled in series between first power supply line 302 and second power supply line 304. Transistor 310′ has a gate terminal that receives emission control signal EM. Storage capacitor Cst1 may have first and second terminals that are coupled to gate and source terminals of drive transistor 312′, respectively.

Transistor 314 may be coupled between reference line 23 and the gate (G) terminal of drive transistor 312′. Transistor 314 has a gate terminal that receives scan control signal SCAN1 and is selectively turned on to set the gate voltage of drive transistor 312′ to predetermined voltage level Vref. Transistor 316′ may be coupled between column line 26 and the anode terminal of diode 300. Transistor 316′ has a gate terminal that receives scan control signal SCAN2 and is selectively turned on to pass a data signal into pixel 22. Transistor 318′ may be coupled between reference voltage line 23 and the anode terminal of light-emitting diode 300. Transistor 318′ has a gate terminal that receives scan control signal SCAN3 and is selectively turned on to reset the anode of diode 300 to reference voltage level Vref.

In the example of FIG. 7, transistors 314 and 312′ may be a semiconducting-oxide transistors, while the other transistors 310′, 316′, and 318′ are silicon transistors (e.g., p-channel LTPS transistors). Since the impedance at the gate (G) of drive transistor 312′ is high, having semi-conducting oxide transistor 314 being coupled to that node may be advantageous to help reduce leakage and power consumption. The drive transistor is typically n-type, so it may be advantageous to keep transistor 312′ as a semiconducting-oxide transistor to simplify fabrication (e.g., forming drive transistor 312′ as an n-type LTPS transistor would necessarily increase the number of lithographic masks and thus increase manufacturing cost). In the arrangement of FIG. 7, data programming and current sensing are also both perform on data lines 26, which can help dramatically reduce array routing complexity and area.

FIG. 8 is a timing diagram illustrating relevant waveforms in operating display pixel 22 shown in FIG. 7. Since transistors 310′, 316′ and 318′ are now p-channel transistors, the corresponding control signals EM, SCAN2, and SCAN3 are active-low signals (i.e., assertion implies that these signals be driven to logic “0”). Prior to time t1, only signal EM is asserted (e.g., emission control signal EM is driven low to logic “0”) while all other scan control signals SCAN1, SCAN2, and SCAN3 are deasserted (e.g., signals SCAN2 and SCAN3 are driven high to logic “1” and signal SCAN1 is driven low to logic “0”) for that row. The period during which signal EM is asserted may be referred to as the emission period T_(EMISSION) or the emission phase.

At time t2, scan signal SCAN1 may be asserted (e.g., driven high) to turn on transistor 314. Activating transistor 314 may allow the gate of drive transistor 312′ to be set to the reference voltage level Vref. At time t3, scan signal SCAN2 may be asserted (e.g., driven low) to turn on transistor 316′. Activating transistor 316′ may allow a data signal presented along line 26 to be loaded into the display pixel (e.g., the data signal may be loaded onto the anode terminal of light-emitting diode 300). The value of the data signal at the falling edge of signal SCAN2 (at time t4) determines what is actually loaded into the display pixel. The period between time t2 and t4 may be referred to as the data programming period T_(DATA_PROGRAMMING) or the data writing phase. The duration of time that the current data signal should be held constant for that row is indicated as one unit programming time 1H (shown as T_(PROG)).

At time t5, signal SCAN1 is deasserted. At this point, the voltage across capacitor Cst1 is fixed (e.g., the voltage stored in Cst1 is equal to the difference between Vref and the programmed data value).

At time t6, only scan signal SCAN3 may be asserted (e.g., driven low) to turn on transistor 318′. Activating transistor 318′ may allow the anode of light-emitting diode 300 to be reset to reference voltage level Vref. Because transistor 314 is turned off, the voltage across capacitor Cst1 cannot change at this time. Thus, resetting the anode voltage level to Vref will simply shift the gate level of drive transistor 312′ up (or down) by the difference between Vref and the data value just loaded into the anode. The gate-to-source voltage of drive transistor 312′ should not change. At time t7, scan signal SCAN3 is deasserted. The period between time t6 and t7 may be referred to as the anode reset period T_(ANODE_RESET) or the anode reset phase. In this example, assertions of scan control signals SCAN1 and SCAN2 are overlapping in time, whereas assertions of scan control signals SCAN1 and SCAN3 are non-overlapping in time.

At time t8, emission control signal EM may be asserted for the emission phase. During the emission phase, current will flow through transistors 310′ and 312′ and light-emitting diode 300, where the magnitude of the current is dependent on the voltage stored across capacitor Cst1. The amount of current will affect the actual luminance of light that is emitted from diode 300.

Configured in this way, pixel 22 of FIG. 7 that is capable of performing anode reset after data loading and before emission eliminates the low gray non-uniformity issue. Moreover, the anode reset operation can help mimic high frequency refresh rates (e.g., 60 Hz, 120 Hz, etc.) even when the display is only operating at low refresh rates (e.g., 30 Hz or below), thus eliminating low refresh rate flicker and improving variable refresh rate index.

FIG. 9A is a diagram showing how at least some row control lines can be shared between pixels in adjacent rows. As shown in FIG. 9A, a gate driver stage such as stage 900 may drive row control signals SCAN1, SCAN3, and EM that is shared between pixels 22-1 and 22-2 and other pixels in the two rows and may also drive signal SCAN2_ODD that is fed only to pixel 22-1 (and other pixels in the first row) and signal SCAN2_EVEN that is fed only to pixel 22-2 (and other pixels in the second row). Gate driver stage 900 may represent one stage in a chain of stages in row driver circuitry 18 (see FIG. 2). While signals SCAN1, SCAN3, and EM can be shared among multiple adjacent rows, signal SCAN2 cannot be shared since it controls the data loading (e.g., different pixels need to be loaded with different data signals to maintain full display resolution).

FIG. 9B is a timing diagram illustrating relevant waveforms in operating display pixels with shared row control lines, as shown in configuration of FIG. 9A. Prior to time t1, only signal EM is asserted (e.g., driven low to logic “1”) while all other scan control signals SCAN1. SCAN2_ODD, SCAN2_EVEN, and SCAN3 are deasserted for those two rows (e.g., active-high signal SCAN1 is driven low to logic “0” while active-low signals SCAN2_ODD. SCAN2_EVEN, and SCAN3 are driven high to logic “1”).

At time t2, shared scan signal SCAN1 may be asserted to turn on transistor 314 in both pixels 22-1 and 22-2 (see FIG. 9A). At time t3, scan signal SCAN2_ODD may be asserted to turn on transistor 316′ in pixel 22-1 (and other pixels along that row). At time t4, scan signal SCAN2_EVEN may be asserted to turn on transistor 316′ in pixel 22-2 (and other pixels along that row). At time t5, signal SCAN2_ODD may be deasserted to latch data signal “X” into pixel 22-1. At time t6, signal SCAN2_EVEN may be deasserted to latch data signal “Y” into pixel 22-2. At time t7, signal SCAN1 may be deasserted.

At time t8, shared scan signal SCAN3 may be asserted to turn on transistor 318 in both pixels 22-1 and 22-2 to perform the anode reset operation. At time t9, signal SCAN3 may be deasserted. At time t10, shared emission control signal EM may be asserted to start the emission phase. The exemplary timing scheme of FIG. 9B in which the emission period is 8H in duration (i.e., eight times the unit data programming period), the SCAN1 period is 4H. and the SCAN2 and SCAN3 periods are 1.5H is merely illustrative and does not serve to limit the scope of the present embodiment. If desired, these periods can be lengthened or shorted and shifted forward or backward in time, so long as data programming and anode reset is properly performed. In general, the sharing of row control lines may be extended to any number of adjacent rows (e.g., row control lines may be shared among three or more rows, four or more rows, five or more rows, etc.).

FIG. 10 is a flow chart of illustrative steps for operating a display pixel of the type shown in connection with FIGS. 2-9 in accordance with at least some embodiments. At step 1000, display pixel 22 may be operated in the emission phase (e.g., by asserting emission control signal EM to allow current to flow through the drive transistor to the OLED while deasserting the scan control signals SCAN1, SCAN2, and SCAN3).

At step 1002, the emission phase may be temporarily suspended (e.g., by temporarily deasserting emission control signal EM to prevent current from flowing through the drive transistor to the OLED).

At step 1004, pixel 22 may be operated in the data programming phase to load compensated image data into the anode terminal (e.g., by pulsing signals SCAN1 and SCAN2 to set the voltage level at the gate terminal of the drive transistor and to load in the compensated data value to the anode terminal, respectively).

At step 1006, pixel 22 may be operated in the anode reset phase so that the anode of the OLED is biased to a predetermined reset/reference voltage level (e.g., by pulsing scan signal SCAN3). Performing anode reset in this way can help eliminate the low gray non-uniformity issues, eliminate low refresh rate flicker, and improve variable refresh rate index. Processing may loop back to step 1000 for successive rows in the display pixel array, as indicated by path 1008.

The exemplary pixel architectures shown in FIGS. 3 and 7 that include five transistors, one capacitor, one emission control line, and three scan control lines are merely illustrative. If desired, the techniques described herein may be extended or applied to pixel structures that include any number of oxide or silicon transistors, any number of capacitors, more than one emission line, less than three scan control lines or more than three scan control lines, and other suitable display pixel architectures.

The foregoing is merely illustrative and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The foregoing embodiments may be implemented individually or in any combination. 

What is claimed is:
 1. A display pixel having a refresh rate, comprising: a light-emitting diode configured to emit light during an emission operation; a drive transistor coupled in series with the light-emitting diode; a data loading transistor coupled to the drive transistor, wherein the data loading transistor is used to perform a data loading operation; and an anode reset transistor coupled to an anode of the light-emitting diode, wherein the anode reset transistor is used to perform anode reset operations at a higher frequency than the refresh rate to reduce flicker.
 2. The display pixel of claim 1, wherein at least some of the anode reset operations reduce low gray level non-uniformity by being performed after the data loading operation and before the emission operation.
 3. The display pixel of claim 1, wherein the frequency at which the anode reset operations are performed is at least two times the refresh rate.
 4. The display pixel of claim 1, wherein the frequency at which the anode reset operations are performed is at least four times the refresh rate.
 5. The display pixel of claim 1, further comprising: a voltage line directly connected to the anode reset transistor; and a semiconducting-oxide transistor connected between the voltage line and a gate terminal of the drive transistor.
 6. The display pixel of claim 5, wherein the anode reset transistor is a silicon transistor.
 7. The display pixel of claim 5, wherein the semiconducting-oxide transistor is an n-type transistor, and wherein the anode reset transistor is a p-type transistor.
 8. The display pixel of claim 5, wherein: the semiconducting-oxide transistor has a gate terminal configured to receive a first scan signal via a first scan line; and the data loading transistor has a gate terminal configured to receive a second scan signal via a second scan line that is different than the first scan line.
 9. The display pixel of claim 8, wherein the anode reset transistor has a gate terminal configured to receive a third scan signal via a third scan line that is different than the first and second scan lines.
 10. The display pixel of claim 5, wherein the semiconducting-oxide transistor and the anode reset transistor are never on at the same time.
 11. A display pixel having a refresh rate, comprising: a light-emitting diode; a drive transistor coupled in series with the light-emitting diode; a first switching transistor directly connected to the drive transistor; a second switching transistor directly connected to the drive transistor; an anode reset transistor coupled to an anode of the light-emitting diode; a first scan line configured to provide a first scan signal to the first switching transistor; a second scan line configured to provide a second scan signal to the second switching transistor; and a third scan line configured to provide a third scan signal to the anode reset transistor, wherein the anode reset transistor is used to reset the anode at a higher frequency than the refresh rate of the display pixel to reduce flicker.
 12. The display pixel of claim 11, wherein the first switching transistor is a semiconducting-oxide transistor.
 13. The display pixel of claim 12, wherein the anode reset transistor is a silicon transistor.
 14. The display pixel of claim 13, wherein the second switching transistor is also a silicon transistor.
 15. The display pixel of claim 11, wherein the first and second scan signals are asserted to perform a data loading operation on the display pixel.
 16. The display pixel of claim 11, wherein the first scan signal is shared between display pixels in adjacent rows.
 17. The display pixel of claim 11, wherein the third scan signal is shared between display pixels in adjacent rows.
 18. A method of operating a display, comprising: loading data into display pixels at a refresh rate, wherein each of the display pixels has a light-emitting diode with an anode; and reducing flicker by resetting the anode in each of the display pixels at a frequency that is at least two times the refresh rate.
 19. The method of claim 18, further comprising: reducing low gray level non-uniformity by resetting the anode after loading data and before an emission period.
 20. The display of claim 18, wherein the refresh rate is less than 30 Hz. 